/*
 * sdramc.h
 *
 *  Created on: Aug 1, 2013
 *      Author: Ken Arok
 *      Revision history:
 *      ---------------------------------------------------------
 *      Date			|	Revised by		|	Description
 *      ---------------------------------------------------------
 *      1. Aug 1, 2013	|	Yosef			| New establishment
 *
 *
 *
 * \brief Hardware Abstraction Layer of SDRAM Controller UC3C0512C
 *
 * Copyright (c) 2013 PT Hanindo Automation Solutions. All rights reserved.
 *
 */

#include "config_board.h"

#if BOARD_1_0_USED

#ifndef SDRAMC_H_
#define SDRAMC_H_

#include <avr32/io.h>
#include "board.h"
#include "config_sdram.h"

#ifdef __cplusplus
extern "C" {
#endif

//! Pointer to SDRAM.
#define SDRAM           ((void *)AVR32_EBI_CS1_0_ADDRESS)

//! SDRAM size.
#define SDRAM_SIZE      (1 << (SDRAM_BANK_BITS + SDRAM_ROW_BITS  + SDRAM_COL_BITS  + (SDRAM_DBW >> 4)))


/*! \brief Initializes the AVR32 SDRAM Controller and the connected SDRAM(s).
 *
 * \param hsb_hz HSB frequency in Hz (the HSB frequency is applied to the SDRAMC
 *               and to the SDRAM).
 *
 * \note HMATRIX and SDRAMC registers are always read with a dummy load
 *       operation after having been written to, in order to force write-back
 *       before executing the following accesses, which depend on the values set
 *       in these registers.
 *
 * \note Each access to the SDRAM address space validates the mode of the SDRAMC
 *       and generates an operation corresponding to this mode.
 */
extern void sdramc_init(unsigned long hsb_hz);

/*! \brief Set the SDRAM in self refresh mode. The SELF REFRESH command can be used to retain
 * data in the SDRAM, even if the rest of the system is
 * powered down. When in the self refresh mode, the
 * SDRAM retains data without external clocking.
 *
 * \note Once the SELF REFRESH command is registered, all
 * the inputs to the SDRAM become "Don't Care" with
 * the exception of CKE, which must remain LOW.
 * Once self refresh mode is engaged, the SDRAM provides its own internal
 * clocking, causing it to perform its
 * own AUTO REFRESH cycles. The SDRAM must remain
 * in self refresh mode for a minimum period equal to
 * tRAS and may remain in self refresh mode for an indefinite
 * period beyond that.
 *
 * \note An example of entering/exiting CPU sleep mode while keeping SDRAM content is :
 * sdram_enter_self_refresh(); SLEEP(AVR32_PM_SMODE_STATIC);  sdram_exit_self_refresh();
 *
 */
void sdram_enter_self_refresh(void);

/*! \brief Exit from the SDRAM self refresh mode, inhibits self refresh mode
 */
void sdram_exit_self_refresh(void);

#ifdef __cplusplus
}
#endif

#endif /* SDRAMC_H_ */

#endif /* BOARD_1_0_USED */
